1. Technical Field
The present disclosure relates to electronic systems and, more particularly, to packaging of electronic systems.
2. Discussion of Related Art
In the computer industry, packaging methods include building circuits forming a system on a single die, referred to as a SoC (System on Chip) device, building circuits forming a system on two or more chips according to chip device type, or packaging each chip into an electronic package and later assembling them on an organic substrate or a printed circuit board (PCB). Chips, such as SoC devices, may be used for high-performance computing solutions or complex combined technology solutions. SoC implementations can result in large die sizes and drive semiconductor die costs up due to additional process steps and complexity. The ability to process multiple complex mixed logic and memory devices as well as other technologies on one wafer may not lead to a robust, high-yield, and low-cost product due to, for example, the complexity of each function not being common with other circuitry or unique processes to obtain system-level functionality.
The gap between processor speeds and memory performance, sometimes referred to as the “memory wall” problem, has become an obstacle to improved computer system performance. One reason for this difficulty is that the memory system resides “off-chip” and packaging constraints limit what can be accomplished to improve the average time to access memory.
One proposed approach to solve this difficulty uses multiple cache levels integrated into a single processor die. This approach has the disadvantage that the processor die becomes large and therefore expensive. Typically, high-end processor chips are spatially dominated by memory allocated for these cache levels.
Memory latency, which refers to the time between the initiation of a memory request and its completion, and bandwidth, which refers to the rate at which the memory system can service requests from the processor, are closely related. Bandwidth is one bottleneck in the performance of a memory system. It is desirable to ensure that the flow of data from memory to the processor is fully balanced, thus increasing overall performance by making efficient use of the processor. One approach to balancing the flow of data is to place a large amount of memory in close proximity to the processor and to allow that memory to communicate with the processor through a wider bus than is typically used (e.g., 1024 channels instead of 16, 32 or 64 running at DDR). Attempting to embed a large amount of memory on the processor chip, as proposed in some SoC designs, would take up chip area while simultaneously driving overall yield down. However, due to aggressive groundrule targets in the future and die yield considerations, it is advantageous for the processor to be as small as is practically permitted by power density and thermal design considerations.
Various techniques to provide redundancy in wiring for interconnection of transistors and to provide a module level cooling solution by leveraging a silicon substrate use a passive silicon substrate as an interconnection to a system.
Microwave silicon devices and low loss transmission lines may be integrated using a highly doped silicon wafer by placing active circuits in single crystal silicon and transmission lines using polycrystalline silicon. This method provides means for microwave transmission between moat regions with active devices and high resistivity regions surrounding each moat region on the semiconductor device but does not provide for modular design (reuse of prior designs), lower power or improved performance at lower cost for system level applications.
Monolithic microwave integrated circuits (MMIC) use high resistivity silicon which may have MMIC placed into etched recesses in the silicon. In this case, gallium arsenide (GaAs) devices are placed into the etched recesses and then interconnected to provide function. For example, MMIC solutions have been used to connect GaAs for microwave applications.
Stacked IC structures, which may provide increased integration due to historical limitations with SOI (silicon on insulator) technology, have been used for memory applications. For example, a method of forming a three-dimensional stacked IC on a base plate is known. A three-dimensional stacked IC may include a unit semiconductor IC, which has constituent ICs formed on one or both surfaces of a substrate. By stacking a plurality of unit ICs on the base plate, a very large scale IC can be fabricated. This method can be applied to the fabrication of a ROM structure such as a PROM or MASK ROM, using single unit semiconductor ICs, wherein a wiring for the ROM can be formed on the second surface of the substrate.
In these methods for producing chip-stacks, 3D integration of die is typically limited to memory products including Flash, SRAM and DRAM, which are edge wire-bonded. These methods do not address the memory bottleneck.
Therefore, a need exists for new packaging techniques to increase the bandwidth to main memory while also reducing the latency to memory.